JPH041501B2 - - Google Patents

Info

Publication number
JPH041501B2
JPH041501B2 JP57042179A JP4217982A JPH041501B2 JP H041501 B2 JPH041501 B2 JP H041501B2 JP 57042179 A JP57042179 A JP 57042179A JP 4217982 A JP4217982 A JP 4217982A JP H041501 B2 JPH041501 B2 JP H041501B2
Authority
JP
Japan
Prior art keywords
conductive pattern
semiconductor element
semiconductor device
frame
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57042179A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58159355A (ja
Inventor
Eiji Hagimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4217982A priority Critical patent/JPS58159355A/ja
Publication of JPS58159355A publication Critical patent/JPS58159355A/ja
Publication of JPH041501B2 publication Critical patent/JPH041501B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145Organic substrates, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP4217982A 1982-03-17 1982-03-17 半導体装置の製造方法 Granted JPS58159355A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4217982A JPS58159355A (ja) 1982-03-17 1982-03-17 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4217982A JPS58159355A (ja) 1982-03-17 1982-03-17 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58159355A JPS58159355A (ja) 1983-09-21
JPH041501B2 true JPH041501B2 (en]) 1992-01-13

Family

ID=12628757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4217982A Granted JPS58159355A (ja) 1982-03-17 1982-03-17 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58159355A (en])

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038842A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd ピングリッドアレイ型半導体パッケージ
JPS6059756A (ja) * 1983-09-12 1985-04-06 Ibiden Co Ltd プラグインパッケ−ジとその製造方法
JPS6095943A (ja) * 1983-10-31 1985-05-29 Ibiden Co Ltd プラグインパツケ−ジとその製造方法
JPS6095944A (ja) * 1983-10-31 1985-05-29 Ibiden Co Ltd プラグインパツケ−ジとその製造方法
JPS60101998A (ja) * 1983-11-07 1985-06-06 イビデン株式会社 プラグインパツケ−ジとその製造方法
JPS60241244A (ja) * 1984-05-16 1985-11-30 Hitachi Micro Comput Eng Ltd ピングリッドアレイ型半導体装置の製造方法
JPS6194359U (en]) * 1984-11-27 1986-06-18
FR2575331B1 (fr) * 1984-12-21 1987-06-05 Labo Electronique Physique Boitier pour composant electronique
US4661192A (en) * 1985-08-22 1987-04-28 Motorola, Inc. Low cost integrated circuit bonding process
JPS62194655A (ja) * 1985-11-20 1987-08-27 アンプ―アクゾ コーポレイション 電子装置用接続パツケ−ジ及びその製造方法
JPS62248244A (ja) * 1986-04-21 1987-10-29 Hitachi Cable Ltd Pga用リ−ドフレ−ム
JPH0821672B2 (ja) * 1987-07-04 1996-03-04 株式会社堀場製作所 イオン濃度測定用シート型電極の製造方法
US5255430A (en) * 1992-10-08 1993-10-26 Atmel Corporation Method of assembling a module for a smart card
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5926618Y2 (ja) * 1979-12-11 1984-08-02 パイオニア株式会社 スル−ホ−ル基板

Also Published As

Publication number Publication date
JPS58159355A (ja) 1983-09-21

Similar Documents

Publication Publication Date Title
US9013030B2 (en) Leadframe, semiconductor package including a leadframe and method for producing a leadframe
US5841183A (en) Chip resistor having insulating body with a continuous resistance layer and semiconductor device
JPH041501B2 (en])
US6486551B1 (en) Wired board and method of producing the same
JPH0570316B2 (en])
US20050189627A1 (en) Method of surface mounting a semiconductor device
KR100226335B1 (ko) 플라스틱 성형회로 패키지
US8697496B1 (en) Method of manufacture integrated circuit package
KR970000219B1 (ko) 반도체 장치 및 그 제조 방법
US6618269B2 (en) Discrete circuit component and process of fabrication
JP3652102B2 (ja) 電子回路モジュール
JPH1126648A (ja) 半導体装置およびそのリードフレーム
JP2602834B2 (ja) 半導体装置
JP3466354B2 (ja) 半導体装置
JP2612468B2 (ja) 電子部品搭載用基板
JPH0228356A (ja) 表面実装型半導体装置及びその製造方法
JPH06821Y2 (ja) 半導体装置の実装構造
JP2822446B2 (ja) 混成集積回路装置
JPH0793402B2 (ja) 半導体装置
JPH07226454A (ja) 半導体装置
JP4311294B2 (ja) 電子装置およびその製造方法
JPH0685165A (ja) 半導体装置及び半導体装置の製造方法
JP2536568B2 (ja) リ―ドフレ―ム
JP2516394Y2 (ja) 半導体装置
JPH07307408A (ja) Icパッケージおよびその組立方法